The present invention relates to metal oxide semiconductor (MOS) image sensors and, more particularly, to logarithmic response image sensors.
Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) sensor has made possible the manufacture of relatively low cost and small hand-held video cameras. Nevertheless, the solid-state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive.
An alternative low cost technology to CCD integrated circuits is the metal oxide semiconductor (MOS) integrated circuit. Not only are imaging devices using MOS technology less expensive to manufacture relative the CCD imaging devices, for certain applications MOS devices are superior in performance. For example, the pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors. In addition, the signal processing logic necessary can be integrated alongside the imaging circuitry, thus allowing for a single integrated chip to form a complete stand alone imaging device.
Two of the categories of CMOS image sensors are linear and logarithmic. In linear sensors, the exposure to light generates a small current in a photosensitive device (such as an inversely polarized photodiode), which is used to charge or discharge a capacitor during a fixed time interval. The voltage on the capacitor after the integration time is proportioned to the incident light intensity and the fixed integration time.
In logarithmic sensors, the current in the photosensitive device produced by the incident light is measured directly. The current is usually converted to voltage through a MOS transistor. This transformation follows a logarithmic function, and can have a very high dynamic range (on the order of 100-120 dB or higher).
FIG. 1 shows a basic prior art logarithmic sensing cell. FIG. 1 has been reproduced from FIG. 4 of xe2x80x9cDesign of a Foveated Log-Polar Image Sensor in Standard CMOS Technologyxe2x80x9d (F. Pardo et al., Design of Integrated Circuits and Systems, DCIS ""96, Sitges, Spain, November 1996). The following description is taken from that reference and explains how the cell works.
The current generated by the light in the photodiode flows through the transistor M1A. This current is very small (between pico and nano amperes), biasing the transistor in its weak inversion region. The second transistor M2A is just a source follower. In the weak inversion region, the simplified expression for the voltage between gate and source is:                               V          gs                =                                            k              ⁢                              xe2x80x83                            ⁢              T                        q                    ⁢          ln          ⁢                      xe2x80x83                    ⁢                      (                                          L                W                            ⁢                                                I                  d                                                  I                  do                                                      )                                              (        1        )            
where Vgs is the gate-source voltage, Id is the drain current, W and L are the width and length of the transistor channel, T is the temperature, and k, q and Ido are constants. From this expression, the logarithmic dependency of the voltage with the current can be seen. It directly means that the response (voltage) is logarithmic with the incident light intensity (current).
Other prior art circuits have attempted to improve the light sensitivity of the basic logarithmic sensing cell. U.S. Pat. No. 5,933,190, to Dierickx et al., shows several circuits designed for this purpose. In a first embodiment, the ""190 patent proposes increasing the lengths of the gates of transistors such as the load transistor in a circuit similar to FIG. 1. As a result of this increase in gate length, it is stated that the load transistor will saturate at lower current densities, and an increase in the sensitivity of the pixel for lower light intensities (current densities) will be achieved. This is based on the premise that the sensitivity of pixels at low light intensities may be limited by the leakage current through the load transistor.
Another embodiment in the ""190 patent is shown in FIG. 4, which has been reproduced as FIG. 2 herein. As illustrated in FIG. 2, the drain of the load transistor M1B is not directly tied to the output signal supply. The read-out means consists of a second MOSFET M2B which is not a source follower and finally, a third MOSFET M3B which acts as a switch. A current source IB provides a current with a magnitude in the order of microamperes. The gate of the transistor M3B is tied to the address.
While the photodiode DB can also be considered a current source (of the order of femtoamperes to nanoamperes according to the intensity of light impinging the photodiode) the transistor M3B is conducting the current decharging through the transistor M2B. Such current can be defined by:
I2xcx9cc(VGxe2x88x92Vth)xe2x80x83xe2x80x83(2)
wherein c is a constant value.
As I2 is given by the current source and is more or less a constant, we have then VG also nearly a constant. Therefore, the light acquired by the photodiode DB is converted into a voltage drop across the load transistor M1B. Accordingly, this pixel has similar functions as the one described in FIG. 1. Alternatively, this pixel can also be considered as a simple and classic resistive feedback amplifier.
As discussed in xe2x80x9cOn-Chip Offset Calibrated Logarithmic Response Image Sensorxe2x80x9d (S. Kavadias et al., 1999 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, pp. 68-71), the major drawback of logarithmic CMOS image sensors (such as those illustrated in FIGS. 1 and 2) compared with their linear counterparts is the increased Fixed Pattern Noise (FPN). This noise is caused from the non-uniformities of the parameters associated with the various devices present on the sensor chip. It appears as an offset in the output signal delivered by each pixel. In linear integrating sensors the photocurrent is integrated on a capacitance over a well-defined time period, therefore methods for the elimination of this offset have been proposed based on the readout of the voltage of the integrating capacitance during two states. One widely used technique in linear integrating sensors is xe2x80x9ccorrelated double samplingxe2x80x9d.
Sensors employing pixels with logarithmic response are very attractive devices in applications where a high dynamic range is required. However, they suffer from high FPN due to the non-availability of two distinct pixel levels as in the case of linear integrating sensors. A few prior art circuits have attempted to address the problem of the high FPN in logarithmic image sensors. One general approach has been to develop a known reference for each pixel, against which the output of the signal can be calibrated.
One way to develop a known reference level for each pixel circuit in an array is to use a known reference current to produce an output from the pixel circuit, similar to how the current from a photodiode would produce an output. By using a known reference current for each of the pixel circuits, a reference level for each of the pixel circuits can be obtained. This technique is described in more detail in xe2x80x9cOn-Chip Offset Calibrated Logarithmic Response Image Sensorxe2x80x9d (supra). FIGS. 1 and 2 of that reference have been reproduced as FIGS. 3A and 3B herein.
FIG. 3A shows a basic pixel structure, where transistor M1C acts as the bias of the photodiode and provides the logarithmic response. Transistor M2C is the driver transistor of the on-pixel source follower and transistor M3C is used for row selection. Transistor M4C connects the pixel to the calibration source ICAL which is common for pixels lying on the same column. Transistor M5C connects the output of photodiode DC to the gate of transistor M2C. The calibration process is accomplished in two states. First, transistor M4C is switched off and the pixel voltage is stored. This voltage is logarithmically related to the photocurrent delivered by the photodiode DC. Then transistor M4C is switched on and the pixel output is again sampled and extracted from the previous level. The difference between these two levels has a very small offset, provided that ICAL is much higher than the photocurrent.
As shown in FIG. 3B, the current source designated as ICAL may be implemented using switches and capacitors. This is stated to be preferred because a very good reproducibility can be achieved among columns. The calibration source consisting of a capacitor CCAL and a transistor MCAL used as a switch, is common for each column of pixels. For simplicity only one pixel is drawn.
In a simulation designed to show the results of a pixel similar to that shown in FIG. 3B, the xe2x80x9cOn-Chip Offset Calibrated Logarithmic Response Image Sensorxe2x80x9d (supra) reference shows that right after the calibration pulse Vc goes high, it forces the pixel output to zero voltage. The photocurrent then charges the calibration capacitance CCAL until Vc goes low again. Then, the pixel voltage returns to its value before the application of the calibration pulse with a time constant determined by the pixel capacitance and the transconductance of the biasing transistor M1C. This transistor is biased in the weak inversion region, therefore its transconductance is proportional to the photocurrent. In the sensor under examination, this time constant for the medium light levels is in the order of a few ms. A very important observation is pointed out, in that for some microseconds right after the instant that VC goes low, the pixel output is independent of the light level. Therefore, the above scheme for FIG. 3B is effectively identical to the calibration with the current source shown in FIG. 3A. The readout sequence is accomplished in two phases. First, before the application of the calibration pulse, the pixel output is sampled and stored. Then, the calibration pulse is applied and a few microseconds later the pixel output is again sampled and stored. The difference between these two stored values depends on the photocurrent and is free from offsets imposed by variations in pixel transistor parameters.
Another prior art circuit intended to deal with the problem of FPN in logarithmic image sensors is shown in xe2x80x9cSelf-Calibrating Logarithmic CMOS Image Sensor with Single Chip Camera Functionalityxe2x80x9d (M. Loose et al., 1999 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, pp. 191-194). FIG. 1 of that reference has been reproduced as FIG. 4 herein. As stated, the calibration concept is based on the fact that the sensor circuit can be stimulated not only by the photodiode but also by a reference current. The output signal corresponding to this reference current is ideally the same for all pixels but in reality differs from pixel to pixel caused by device-to-device variations. A differential amplifier compares the real pixel output to a reference voltage and adjusts the pixel until both voltages are equal. The calibrated pixel state is finally stored on a capacitor working as an analog memory cell.
FIG. 4 shows the schematic diagram of the offset-correcting pixel. The switches S1 to S5 are realized by single MOS transistors. During readout mode, the switch S2 is closed leading to a current path from the photodiode through the transistors M1D and M3D to Vdd. M1D and M3D work in weak inversion and convert the photocurrent into a logarithmic voltage. The pixel output voltage, buffered by transistor M2D, can be read out through the Vout2 line by closing the selection switch S4. By opening S2 and closing S1, S3 and S5, the receptor circuit changes to calibration mode. It is now stimulated by the reference current Iref. The output signal is guided through Vout1 to the input of the calibrating operational amplifier AMPD at the end of each column. This autozeroing amplifier AMPD compares Vout1 to a voltage Vref and produces the correction voltage Vcorr. Since Vcorr is connected to the gate of M3D, a change of this voltage leads to a change in the pixel output voltage. The calibration amplifier AMPD moves Vcorr until the difference between Vout1 and Vref becomes zero. Finally the correction voltage is stored on the capacitor CD by opening S3.
The above prior art methods for developing a reference current in a logarithmic response image sensor have a number of drawbacks. For example, with reference to the column line shown in FIG. 3B for the calibration current, extra power is required by the circuit for charging and discharging any existing capacitance. For example, the extra capacitor CCAL must be charged and discharged each time there is a voltage change on the column line. This results in extra power consumption by the circuit. In addition, the structure itself is an extra column line that is required solely for the purpose of providing the reference current. As stated, the capacitor and switch implementation of FIG. 3B is used to attempt to obtain good reproducibility among the columns, which is relatively difficult to achieve for current sources. As further described with reference to FIG. 4, the setting and control of a reference current can be very difficult.
The present invention is directed to a logarithmic response image sensor that overcomes the foregoing and other disadvantages. More specifically, the present invention is directed to a pixel structure for a CMOS image sensor that can cancel fixed pattern noise due to offset and gain mismatch in a logarithmic response image sensor.
An improved pixel structure for a logarithmic response image sensor is provided. The pixel structure and readout sequence provides a method to get a signal free from offsets and gain mismatch due to non-uniformities in the device parameters.
In accordance with one aspect of the invention, the image sensor includes a calibration transistor in addition to a standard logarithmic response CMOS pixel structure. The calibration transistor receives a calibration signal and operates to cause the image sensor to output a calibration signal level, which can be processed with the sensed signal level to produce an output that is free from offsets and gain mismatch due to non-uniformities in the device parameters.
In accordance with another aspect of the invention, the calibration transistor may be coupled internally within the pixel structure itself, so that an additional column line is not required to produce the calibration signal. In this structure, the calibration transistor may be coupled to the node between the load transistor and the photosensitive device. Thus, when the calibration transistor is biased in the conducting state, at least part of the current that flows through it also flows through the load transistor.
In accordance with another aspect of the invention, the calibration transistor may be coupled to an external column reference voltage line. In this structure, the column reference voltage line is coupled by the calibration transistor to the gate of the third transistor that is coupled in series with the output of the image sensor.
In accordance with another aspect of the invention, the calibration transistor receives the current that it conducts from a voltage line which is coupled to a voltage source, rather than a current source. In this manner, the inherent disadvantages of attempting to utilize a current source for the calibration method, such as the difficulties of controlling the current source, as well as the additional power consumption, are avoided.
It will be appreciated that the disclosed image sensor has numerous advantages over prior art methods and circuits for obtaining a reference signal in a logarithmic response type system. The present invention avoids the control problems, power consumption, and additional circuitry required by the prior art methods.